Enhanced photoluminescence emission from bandgap shifted InGaAs/InGaAsP/InP microstructures processed with UV laser quantum well intermixing

In spite of many years of research, the quantum well intermixing technique has not been able to deliver multibandgap III–V semiconductor wafers at highly attractive costs. We report that UV laser irradiation of InGaAs/InGaAsP/InP quantum well (QW) microstructures in deionized water and rapid thermal annealing (RTA) allows achieving, mask-free, wafers with blueshifted photoluminescence (PL) emission of intensity exceeding almost 10× that of the RTA-only wafers. Our calculations indicate that a ~40 nm thick InOx layer formed on top of the investigated microstructure induces compressive strain in the QW region and leads to this record-high enhanced PL amplitude.

Source:IOPscience

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An investigation of the DC and RF performance of InP DHBTs transferred to RF CMOS wafer substrate *

This paper investigated the DC and RF performance of the InP double heterojunction bipolar transistors (DHBTs) transferred to RF CMOS wafer substrate. The measurement results show that the maximum values of the DC current gain of a substrate transferred device had one emitter finger, of 0.8 μm in width and 5 μm in length, are changed unobviously, while the cut-off frequency and the maximum oscillation frequency are decreased from 220 to 171 GHz and from 204 to 154 GHz, respectively. In order to have a detailed insight on the degradation of the RF performance, small-signal models for the InP DHBT before and after substrate transferred are presented and comparably extracted. The extracted results show that the degradation of the RF performance of the device transferred to RF CMOS wafer substrate are mainly caused by the additional introduced substrate parasitics and the increase of the capacitive parasitics induced by the substrate transfer process itself.

Source:IOPscience

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Comparison of on-wafer calibrations for THz InP-based PHEMTs applications

A quantitative comparison of multiline TRL (thru-reflect-line) and LRM (line-reflect-match) on-wafer calibrations for scattering parameters (S-parameters) measurement of InP-based PHEMTs is presented. The comparison is undertaken for the first time and covers a frequency range from 70 kHz to 110 GHz. It is demonstrated that the accuracy of multiline TRL and LRM calibration is in good agreement. Both methods outperform the conventional SOLT calibration in the full frequency band up to 110 GHz. Then the excellent RF performance is obtained by extrapolation on the basis of inflection point, including a maximum current gain cut-off frequency ft of 247 GHz and a maximum oscillation frequency fmax of 392 GHz. The small-signal model based on LRM calibration is established as well. The S-parameters of the model are consistent with the measured from 1 to 110 GHz.

Source:IOPscience

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InP-Si BiCMOS Heterointegration Using a Substrate Transfer Process

Broadband transmitters for radio links in the mm-wave range are key building blocks for future wireless communication systems. In this work such components are to be realized by means of an InP-on-BiCMOS technology. This allows the combination of the favorable power performance of III-V transistors with the advantages of BiCMOS circuits such as complexity and integration density.This helps to avoid critical performance trade-offs compared to the pure III-V or BiCMOS versions. The heterointegration technology allows the integration of sub-mm-wave front-ends together with control logics and other lower-frequency components on a single chip. This drastically reduces packaging efforts. The strategy is to rely on BiCMOS as far as possible and to apply III-V elements only for functions for which they show clear superiority. In a first run the passive elements and the dc- and rf-interconnects between InP and BiCMOS were tested. This test showed the feasibility of the wafer bond process for the heterointegration of InP and BiCMOS. For that purpose a five metal layer Al back-end with silicon dioxide as interlayer dielectric was built on the silicon wafer. A three layer metallization (Au) in benzocyclobutene (BCB) as insulating dielectric represented the environment for the InP-HBTs. Thin film micro strip lines and special designed interconnects between the two metallization systems were characterized in dependence of frequencies up to 100 GHz to estimate the insertion losses.

Source:IOPscience

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Quantitative Analysis of the Metallic Contamination On GaAs and InP Wafers by TXRF and ICPMS Techniques

The quantitative analysis of the metallic contaminants both by chemical collection coupled to ICPMS and TXRF were implemented on GaAs and InP 100mm wafers. VPD-DC-ICPMS and LPD-ICPMS were developed respectively for GaAs and InP substrates. These methods present CE higher than 85% for usual metallic contaminants except for Cu & noble metals, and very sensitive detection thresholds are reached (108 to 1011 at/cm²). TXRF analysis conditions were optimized on both substrates. Na, Mg, Al, Ir and Ge on GaAs and K, Ca, Pd and Ag on InP are not analyzable due to substrate interferences. TXRF calibration was carried out from intentionally contaminated wafers in reference to ICPMS methods. Finally, TXRF enables to reach interesting detection limits (1010 to 1012at/cm² range) and is able to measure Cu and some noble metals.

Source:IOPscience

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Kinetic study of hydrogen lateral diffusion at high temperature in a directly-bonded InP-SiO2/Si substrate

Hybrid integration of III–V materials onto silicon by direct bonding technique is a mature and promising approaches to develop advanced photonic integrated devices into the silicon photonics platform. In this approach, the III–V material stack is grown on an InP wafer in a unique epitaxial step prior to the direct bonding process onto the silicon-on-insulator wafer. Currently, no additional epitaxial regrowth steps are implemented after bonding. This can be seen as a huge limitation as compared to the III–V on III–V wafer mature technology where multi-regrowth steps are most often implemented. In this work, we have studied the material behavior of an InP membrane on silicon (InPoSi) under epitaxial regrowth conditions by metal-organic vapor phase epitaxy (MOVPE). MOVPE requires high-temperature elevation, typically above 600 °C. We show for the first time the appearance of voids at 400 °C in an InP seed (100 nm) directly-bonded onto a thermally oxidized Si substrate despite the use of a thick SiO2 oxide (200 nm) at the bonding interface. This phenomenon is explained by a weakening of the bonding interface while high-pressurized hydrogen is present. A kinetic study of the hydrogen lateral diffusion is carried out, enabling the assessment of its lateral diffusion length. To overcome the void formation, highly efficient outgassing trenches after bonding are demonstrated. Finally, high-quality AlGaInAs-based multi-quantum well (MQW) heterostructure surrounded by two InP layers was grown by MOVPE on InPoSi template patterned with outgassing trenches. This process is not only compatible with MOVPE regrowth conditions (650 °C under PH3) but also with conventional fabrication processes used for photonic devices.

Source:IOPscience

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Photoluminescence of Semi‐insulating InP Wafers Prepared by Two‐Step Wafer Annealing

InP wafers with very low residual Fe concentrations were subjected to a two‐step wafer annealing procedure and were then measured by photoluminescence. A sharp line at 1.3618 eV was clearly observed after the first step high temperature annealing, and was largely reduced after the second step medium temperature annealing. This sharp line seems to be due to vacancy‐related defects. The reduction may cause the improvement of the electrical property uniformity.

Source:IOPscience

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Optical Investigations of Directly Wafer-Bonded InP–GaAs Heterojunctions

The optical characteristics of directly wafer-bonded InP–GaAs heterojunctions have been investigated. By designing the bonding interface at standing-wave antinode, its influence on optical performances of bonded structures is magnified, which facilitates experimental detection using optical methods. Wavelength blueshift and reflectivity falling at the resonance mode were observed in wafer-bonded InP–GaAs heterostructures. Numerical analysis suggests that two effects involving thickness change of interfacial bonding layers and extra optical loss introduced by bonded junctions are responsible for the experimental observations, and these effects can be attenuated by lowering anneal temperatures and incorporating an  superlattice into the surface of InP-based materials. The results are useful for designing effective optical characteristics of wafer-bonded device structures.

Source:IOPscience

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Bromine/Methanol Polishing of InP Substrates

The dependence of bromine/methanol polishing of <100>  on a number of major parameters—wafer area, applied pressure, rotational speed, and flow rate—has been studied in detail. For a one volume percent solution, the polishing rate is linearly proportional to flow rate, inversely proportional to wafer area, and independent of pressure and rotational speed. Hence, under our experimental conditions, the polishing action is limited by transport of Br to the wafer surface, and mechanical abrasion of the wafer by the pad is insignificant. The surface topography is controlled by the wafer size and by a parameter , defined as the ratio of flow rate/wafer area. For , free etching occurs and pits form on the wafer surface. In addition, as lateral dimensions of the wafer shrink to < ~2 cm, surface topography degrades due to edge effects. Under the proper conditions, polishing rates as high as 6 μm/min may be obtained while maintaining excellent surface topography. The polished wafers are free of subsurface damage, as revealed by defect etching.

Source:IOPscience

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Integration of InP and InGaAs on 300 mm Si Wafers Using Chemical Mechanical Planarization

Integration of III-V high mobility channel materials in complementary metal oxide semiconductors (CMOS) and III-V photonic materials for integrated light sources on Si substrates requires low defect density III-V buffer layers in order to enable epitaxial growth of high crystal quality active layers. For the fabrication of In0.53Ga0.47As n-channel MOSFET on Si, a lattice matched InP buffer layer is one of the most effective approaches when used in combination with the aspect ratio trapping technique, an integration method known for reducing the density of defects formed during relaxation of strain induced by the lattice mismatch between InP and Si. The InP buffer should be planarized in order to improve thickness uniformity and roughness before subsequent deposition of active layers. In this work we discuss the development of InP planarization on 300 mm Si wafers and investigate slurry composition effects on the final oxide loss and condition of the InP surface. To further explore viability of this approach we deposited an epitaxial In0.53Ga0.47As n-MOS channel layer on top of the planarized InP buffer.

Source:IOPscience

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Mechanical Thinning of InP Wafer by Grinding

 wafers of 2 in. diameter have been successfully ground to a thickness of 100 μm by mechanical grinding with cup‐type diamond wheels. This process can be applied, for the first time, to the mass production of  optoelectronic devices, similar to the technology for  devices based on the wafer‐rotating downfeed grinding method. The phenomena occurring in the grinding of  were similar to those of , such as a rapid transition between mirror grinding and rough grinding, and a large wafer bow. However, the deformed layer due to the grinding of  was discovered to be thicker than that of , because  is a little more fragile. Still, it was thin enough, less than 1.5 μm, to be eliminated by slight chemical etching. The finished surface roughness in mirror grinding was also greater, but 0.15 μm  was obtained with 3 μm diamond grains, which is small enough to be applied in device fabrications.

Source:IOPscience

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Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915°C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO2 and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES.

Source:IOPscience

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Enhanced bonding strength of InP/Si chip-on-wafer by plasma-activated bonding using stress-controlled interlayer

To realize next-generation photonic integrated circuits based on the III–V/Si hybrid integration platform using chip-on-wafer (CoW) direct bonding technologies, high-yield collective bonding of InP chips on Si substrates with a high bonding strength is required. This study demonstrates high-yield InP/Si CoW plasma-activated bonding using a chip holder with pockets, the depth of which is precisely controlled. Additionally, finite element simulations are used to determine that the stress-controlled interlayer consisting of InP-based epitaxial layers with tensile strain effectively suppresses stress at the InP/Si bonding interface, which affects the bonding strength. Thus, a high bonding strength of 20 MPa in 2 mm × 2 mm InP chips on the Si substrate was achieved by introducing a superlattice structure consisting of GaInAsP and InP (with tensile strain) as the stress-controlled interlayer.

Source:IOPscience

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Fabrication of InP/SiO2/Si Substrate using Ion-Cutting Process and Selective Chemical Etching

In this study, an InP layer was transferred onto a Si substrate coated with a thermal oxide, through a process combining ion-cutting process and selective chemical etching. Compared with conventional ion-cutting of bulk InP wafers, this layer transfer scheme not only takes advantage of ion- cutting by saving the remaining substrates for reuse, but also takes advantage of selective etching to improve the transferred surface conditions without using the chemical and mechanical polishing. An InP/InGaAs/InP heterostructure initially grown by MOCVD was implanted with H+ ions. The implanted heterostructure was bonded to a Si wafer coated with a thermal SiO2 layer. Upon subsequent annealing, the bonded structure exfoliated at the depth around the hydrogen projected range located in the InP substrate. Atomic force microscopy showed that after selective chemical etchings on the as-transferred structure, a final structure of InP/SiO2/Si was obtained with a relatively smooth surface.

Source:IOPscience

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