Geometry and Thermal Stress Analysis of In-plane Outgassing Channels in Al2O3-Intermediated InP (Die)-to-Si (Wafer) Bonding

Thermal-mechanical characteristics and outgassing efficiency of integrated in-plane outgassing channels (IPOCs) at Al2O3-intermediated InP (die)-to-Si (wafer) bonding interface is investigated. The IPOCs are introduced and investigated via both multi-physics simulation and experimental demonstration. Thermal stress simulation indicates that Al2O3 bonding layer efficiently mitigates the stress as observed at top InP surface, compared to that of conventional SiO2 intermediate layer. By introducing IPOCs, the thermal stress decreases with increasing IPOC spacing-to-width (S/W) ratio. Experimentally, high quality InP/Al2O3/Si direct bonding is firstly demonstrated. Seamless bonding interface is observed, along with reasonable bond shear strength of 2.57 MPa and minimal residual stress in the transferred InP layer. Efficiency of the IPOCs is then evaluated by comparing interfacial void densities of InP bonded on dimension-varied-IPOC-patterned Si. A significant void density reduction up to two orders of magnitude is observed, with a decreasing S/W ratio. An optimal S/Wratio of 2.5 is therefore proposed to compromise between the thermal stress degradation (~10%) and outgassing efficiency improvement (~90% void density suppression). This work is thus significant as it could provide guidelines to establish high quality hybrid-integrated optoelectronic devices for Si photonic applications.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Low temperature InP layer transfer onto Si by helium implantation and direct wafer bonding

Helium implantation-induced layer splitting of InP in combination with direct wafer bonding was utilized to achieve low temperature layer transfer of InP onto Si(1 0 0) substrates. InP(1 0 0) wafers with 4 inch diameter were implanted by 100 keV helium ions with a dose of 5 × 1016 cm−2. Then the as-implanted wafers were coated with a spin-on glass (SOG) oxide having a thickness of 150 nm. The SOG coated InP wafers were subsequently bonded to thermally oxidized Si(1 0 0) handle wafers and the bonded wafer pairs were annealed at 200 °C for 20 h to achieve InP layer transfer onto Si(1 0 0) wafers, enabling monolithic integration of InP with Si. Cross-sectional transmission electron microscope images of the transferred InP layers revealed that the layers were about 650 nm thick, which consisted of a heavily damaged InP layer about 300 nm thick directly at the surface and a remaining 350 nm thick layer with considerably less damage.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Wafer Stage Staining Technique for Detection of Zn Out‐Diffusion in InGaAsP / InP Lasers

We have developed a novel staining technique to detect Zn out‐diffusion from the cladding layer into the semi‐insulating region in  laser structures. In this staining technique an Au (400Å thick) coating was applied to wafer and an aqueous  solution was used to stain the Au‐coated wafer. This technique can clearly resolve the Zn out‐diffusion profile in laser structures, and it cannot be achieved by the conventional  staining process. This is the only available technique one can use to detect zinc out‐diffusion from the p‐cladding layer into semi‐insulating  at the wafer stage and prior to device fabrication. Characterization of zinc diffusion by our technique can provide crystal growers with a timely feedback to further optimize the growth parameters.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Bonding temperature dependence of GaInAsP/InP laser diode grown on hydrophilically directly bonded InP/Si substrate

The bonding-temperature-dependent lasing characteristics of 1.5 a µm GaInAsP laser diode (LD) grown on a directly bonded InP/Si substrate were successfully obtained. We have fabricated the InP/Si substrate using a direct hydrophilic wafer bonding technique at bonding temperatures of 350, 400, and 450 °C, and deposited GaInAsP/InP double heterostructure layers on this InP/Si substrate. The surface conditions, X-ray diffraction (XRD) analysis, photoluminescence (PL) spectra, and electrical characteristics after the growth were compared at these bonding temperatures. No significant differences were confirmed in X-ray diffraction analysis and PL spectra at these bonding temperatures. We realized the room-temperature lasing of the GaInAsP LD on the InP/Si substrate bonded at 350 and 400 °C. The threshold current densities were 4.65 kA/cm2 at 350 °C and 4.38 kA/cm2 at 400 °C. The electrical resistance was found to increase with annealing temperature.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com