Transport properties of metal–semiconductor junctions on n-type InP prepared by electrophoretic deposition of Pt nanoparticles

Electrical properties of highly rectifying Pt/InP junctions fabricated by electrophoretic deposition of Pt nanoparticles are investigated at different temperatures by the measurement of current–voltage and capacitance–voltage characteristics. The forward I–V characteristics of the junction are described by thermionic emissions theory at low forward bias (3kT/q < V < 0.2 V) and by tunnelling current transport through the narrowed space charge region at forward bias V > 0.2 V. The reverse I–V characteristics are analysed in the scope of the thermionic emission model in the presence of shunt resistance. Electrical characteristics of these diodes are sensitive to gas mixtures with a low hydrogen concentration and show an extremely fast response and recovery time.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Room-Temperature Annealing Effects on Radiation-Induced Defects in InP Crystals and Solar Cells

Remarkable defect annealing in both p-type and n-type InP following 1-MeV electron irradiation has been observed at room temperature, resulting in the recovery of InP solar cell properties. The room-temperature annealing characteristics of radiation-induced defects in InP were studied by measuring InP solar cell photovoltaic properties in conjunction with deep-level transient spectroscopy. The recovery of InP solar cell radiation damage is found to be due mainly to the room-temperature annihilation of radiation-induced recombination centers such as an H4 trap (Ev+0.37 eV) in p-InP. Moreover, the room-temperature annealing rate of radiation-induced defects in InP was found to be proportional to the 2/3 power of the carrier concentration. Additionally, a model has been considered in which point defects diffuse to sinks through impurities so as to annihilate and bind with impurities, thus forming point defect-impurity complexes.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Efficient ion-slicing of InP thin film for Si-based hetero-integration

Integration of high quality single crystalline InP thin film on Si substrate has potential applications in Si-based photonics and high-speed electronics. In this work, the exfoliation of a 634 nm crystalline InP layer from the bulk substrate was achieved by sequential implantation of He ions and H ions at room temperature. It was found that the sequence of He and H ion implantations has a decisive influence on the InP surface blistering and exfoliation, which only occur in the InP pre-implanted with He ions. The exfoliation efficiency first increases and then decreases as a function of H ion implantation fluence. A kinetics analysis of the thermally activated blistering process suggests that the sequential implantation of He and H ions can reduce the InP thin film splitting thermal budget dramatically. Finally, a high quality 2 inch InP-on-Si(100) hetero-integration wafer was fabricated by He and H ion sequential implantation at room temperature in combination with direct wafer bonding.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Simulation for silicon-compatible InGaAs-based junctionless field-effect transistor using InP buffer layer

In this paper, we present the optimized performances of indium gallium arsenide (InGaAs)-based compound junctionless field-effect transistors (JLFETs) using an indium phosphide (InP) buffer layer. The proposed InGaAs-InP material combination with little lattice mismatch provides a significant improvement in current drivability securing various potential applications. Device optimization is performed in terms of primary dc parameters and characterization is investigated by two-dimensional (2D) technology computer-aided design simulations. The optimization variables were the channel doping concentration (Nch), the buffer doping concentration (Nbf), and the channel thickness (Tch). For the optimally designed InGaAs JLFET, on-state current (Ion) of 325 µA µm−1, subthreshold swing (S) of 80 mV dec−1, and current ratio (Ion/Ioff) of 109 were obtained. In the end, the results are compared with the data of silicon (Si)-based JL MOSFETs to confirm the improvements.

Source:IOPscience

For more information, please visit our website:  www.semiconductorwafers.net,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com