wafers of 2 in. diameter have been successfully ground to a thickness of 100 μm by mechanical grinding with cup‐type diamond wheels. This process can be applied, for the first time, to the mass production of 
optoelectronic devices, similar to the technology for 
devices based on the wafer‐rotating downfeed grinding method. The phenomena occurring in the grinding of 
were similar to those of 
, such as a rapid transition between mirror grinding and rough grinding, and a large wafer bow. However, the deformed layer due to the grinding of 
was discovered to be thicker than that of 
, because 
is a little more fragile. Still, it was thin enough, less than 1.5 μm, to be eliminated by slight chemical etching. The finished surface roughness in mirror grinding was also greater, but 0.15 μm 
was obtained with 3 μm diamond grains, which is small enough to be applied in device fabrications.
Source:IOPscience
The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915°C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO2 and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES.
Source:IOPscience
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To realize next-generation photonic integrated circuits based on the III–V/Si hybrid integration platform using chip-on-wafer (CoW) direct bonding technologies, high-yield collective bonding of InP chips on Si substrates with a high bonding strength is required. This study demonstrates high-yield InP/Si CoW plasma-activated bonding using a chip holder with pockets, the depth of which is precisely controlled. Additionally, finite element simulations are used to determine that the stress-controlled interlayer consisting of InP-based epitaxial layers with tensile strain effectively suppresses stress at the InP/Si bonding interface, which affects the bonding strength. Thus, a high bonding strength of 20 MPa in 2 mm × 2 mm InP chips on the Si substrate was achieved by introducing a superlattice structure consisting of GaInAsP and InP (with tensile strain) as the stress-controlled interlayer.
Source:IOPscience
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In this study, an InP layer was transferred onto a Si substrate coated with a thermal oxide, through a process combining ion-cutting process and selective chemical etching. Compared with conventional ion-cutting of bulk InP wafers, this layer transfer scheme not only takes advantage of ion- cutting by saving the remaining substrates for reuse, but also takes advantage of selective etching to improve the transferred surface conditions without using the chemical and mechanical polishing. An InP/InGaAs/InP heterostructure initially grown by MOCVD was implanted with H+ ions. The implanted heterostructure was bonded to a Si wafer coated with a thermal SiO2 layer. Upon subsequent annealing, the bonded structure exfoliated at the depth around the hydrogen projected range located in the InP substrate. Atomic force microscopy showed that after selective chemical etchings on the as-transferred structure, a final structure of InP/SiO2/Si was obtained with a relatively smooth surface.
Source:IOPscience
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