The optical characteristics of directly wafer-bonded InP–GaAs heterojunctions have been investigated. By designing the bonding interface at standing-wave antinode, its influence on optical performances of bonded structures is magnified, which facilitates experimental detection using optical methods. Wavelength blueshift and reflectivity falling at the resonance mode were observed in wafer-bonded InP–GaAs heterostructures. Numerical analysis suggests that two effects involving thickness change of interfacial bonding layers and extra optical loss introduced by bonded junctions are responsible for the experimental observations, and these effects can be attenuated by lowering anneal temperatures and incorporating an superlattice into the surface of InP-based materials. The results are useful for designing effective optical characteristics of wafer-bonded device structures.
The dependence of bromine/methanol polishing of <100> on a number of major parameters—wafer area, applied pressure, rotational speed, and flow rate—has been studied in detail. For a one volume percent solution, the polishing rate is linearly proportional to flow rate, inversely proportional to wafer area, and independent of pressure and rotational speed. Hence, under our experimental conditions, the polishing action is limited by transport of Br to the wafer surface, and mechanical abrasion of the wafer by the pad is insignificant. The surface topography is controlled by the wafer size and by a parameter , defined as the ratio of flow rate/wafer area. For , free etching occurs and pits form on the wafer surface. In addition, as lateral dimensions of the wafer shrink to < ~2 cm, surface topography degrades due to edge effects. Under the proper conditions, polishing rates as high as 6 μm/min may be obtained while maintaining excellent surface topography. The polished wafers are free of subsurface damage, as revealed by defect etching.
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Integration of III-V high mobility channel materials in complementary metal oxide semiconductors (CMOS) and III-V photonic materials for integrated light sources on Si substrates requires low defect density III-V buffer layers in order to enable epitaxial growth of high crystal quality active layers. For the fabrication of In0.53Ga0.47As n-channel MOSFET on Si, a lattice matched InP buffer layer is one of the most effective approaches when used in combination with the aspect ratio trapping technique, an integration method known for reducing the density of defects formed during relaxation of strain induced by the lattice mismatch between InP and Si. The InP buffer should be planarized in order to improve thickness uniformity and roughness before subsequent deposition of active layers. In this work we discuss the development of InP planarization on 300 mm Si wafers and investigate slurry composition effects on the final oxide loss and condition of the InP surface. To further explore viability of this approach we deposited an epitaxial In0.53Ga0.47As n-MOS channel layer on top of the planarized InP buffer.