Fabrication scheme for heterogenous Si-to-InP circuits on wafer
level is described.
Wafer-to-wafer alignment accuracy better than 4–8 μm after bonding
Interconnects with excellent performance up to 220 GHz
Palladium barrier necessary when combining Al-based technology with
gold based one.
In order to benefit from the material properties of both InP-HBT
and SiGe-BiCMOS technologies we have employed three-dimensional (3D)
Benzocyclobutene (BCB)-based wafer bonding integration scheme. A monolithic
wafer fabrication process based on transfer-substrate technology was developed,
enabling the realization of complex hetero-integrated high-frequency circuits.
Miniaturized vertical interconnects (vias) with low insertion loss and excellent
broadband properties enable seamless transition between the InP and BiCMOS
- Heterojunction bipolar transistors;
- Indium phosphide;
- Monolithic integrated circuits;
- Three-dimensional integrated
- Wafer bonding;
- Wafer scale integration
If you are more interesting in InP wafer, please send emails to us: email@example.com and visit our website: www.powerwaywafer.com